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[IEEE 2012 IEEE Symposium on Computer Applications and Industrial Electronics (ISCAIE) - Kota Kinabalu, Sabah, Malaysia (2012.12.3-2012.12.4)] 2012 International Symposium on Computer Applications and Industrial Electronics (ISCAIE) - Evaluating thread level parallelism based on optimum cache architecture

✍ Scribed by Alipour, Mehdi; Khorramshahi, B. Ali; Karimi, Fatemeh; Mirzaei, Zhila; Vaghari, Aryo

Book ID: 121248080
Publisher: IEEE
Year: 2012
Weight: 366 KB
Category: Article
ISBN: 1467330310
DOI: 10.1109/ISCAIE.2012.6482067

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