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[IEEE 2012 IEEE International Solid- State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2012.02.19-2012.02.23)] 2012 IEEE International Solid-State Circuits Conference - A 32-core RISC microprocessor with network accelerators, power management and testability features

✍ Scribed by Miller, Brian; Brasili, Derek; Kiszely, Tim; Kuhn, Rob; Mehrotra, Rahul; Salvi, Manan; Kulkarni, Mandar; Varadharajan, Anand; Yin, Shi-Huang; Lin, William; Hughes, Adam; Stysiack, Bill; Kandadi, Vasu; Pragaspathi, Ilan; Hartman, Dan; Carlson, David; Yalala, Vishnu; Xanthopoulos, Thucydides; Meninger, Scott; Crain, Ethan; Spaeth, Mark; Aina, Akin; Balasubramanian, Suresh; Vulih, Joe; Tiwary, Pragati; Lin, David; Kessler, Richard; Fishbein, Bruce; Jain, Anil

Book ID: 111876958
Publisher: IEEE
Year: 2012
Weight: 413 KB
Volume: 0
Category: Article
ISBN: 1467303755
DOI: 10.1109/isscc.2012.6176877

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