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[IEEE 2012 IEEE CPMT Symposium Japan (Formerly VLSI Packaging Workshop of Japan) - Kyoto, Japan (2012.12.10-2012.12.12)] 2012 2nd IEEE CPMT Symposium Japan - Three-dimensional integration scheme using hybrid wafer bonding and via-last TSV process

✍ Scribed by Takeda, Kenichi; Aoki, Mayu; Hozawa, Kazuyuki; Furuta, Futoshi; Yanagisawa, Azusa; Kikuchi, Hidekazu; Mitsuhashi, Toshio; Kobayashi, Harufumi

Book ID: 120580514
Publisher: IEEE
Year: 2012
Weight: 663 KB
Category: Article
ISBN: 1467326534
DOI: 10.1109/ICSJ.2012.6523456

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