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[IEEE 2012 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) - Kgs. Lyngby, Denmark (2012.05.7-2012.05.9)] 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems - Tiempo Asynchronous Circuits System Verilog Modeling Language

✍ Scribed by Renaudin, Marc; Fonkoua, Alain

Book ID: 121676285
Publisher: IEEE
Year: 2012
Weight: 219 KB
Category: Article
ISBN: 1467313602
DOI: 10.1109/ASYNC.2012.22

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