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[IEEE 2012 17th Asia and South Pacific Design Automation Conference (ASP-DAC) - Sydney, Australia (2012.01.30-2012.02.2)] 17th Asia and South Pacific Design Automation Conference - Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range

✍ Scribed by Inoue, Keisuke; Kaneko, Mineo

Book ID: 125497228
Publisher: IEEE
Year: 2012
Weight: 158 KB
Category: Article
ISBN: 1467307718
DOI: 10.1109/ASPDAC.2012.6164952

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