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[IEEE 2011 International Symposium on Electronic System Design (ISED) - Kochi, Kerala, India (2011.12.19-2011.12.21)] 2011 International Symposium on Electronic System Design - PVT-tolerant 7-Transistor SRAM Optimization via Polynomial Regression

✍ Scribed by Mohanty, Saraju P.; Kougianos, Elias

Book ID: 126752291
Publisher: IEEE
Year: 2011
Weight: 289 KB
Category: Article
ISBN: 076954570X
DOI: 10.1109/ISED.2011.11

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