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[IEEE 2011 International Conference of Electron Devices and Solid-State Circuits (EDSSC) - Tianjin, China (2011.11.17-2011.11.18)] 2011 IEEE International Conference of Electron Devices and Solid-State Circuits - The verification of network processor Fast Bus Interface using SystemVerilog

✍ Scribed by Pei-Jun, Ma; Wen-Bo, Ma; Kang, Li; Jiang-Yi, Shi; Yong, Jiang

Book ID: 126660639
Publisher: IEEE
Year: 2011
Weight: 252 KB
Category: Article
ISBN: 1457719967
DOI: 10.1109/EDSSC.2011.6117669

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