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[IEEE 2011 IEEE Workshop on Signal Processing Systems (SiPS) - Beirut, Lebanon (2011.10.4-2011.10.7)] 2011 IEEE Workshop on Signal Processing Systems (SiPS) - Reconfigurable cache memory architecture for integral image and integral histogram applications

✍ Scribed by Hsu, Po-Hao; Chien, Shao-Yi

Book ID: 115526424
Publisher: IEEE
Year: 2011
Weight: 541 KB
Volume: 0
Category: Article
ISBN: 1457719193
DOI: 10.1109/sips.2011.6088966

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