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[IEEE 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) - Seoul, Korea (South) (2011.08.7-2011.08.10)] 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) - Reduced-memory forward-backward check node processing architecture for non-binary LDPC decoding

✍ Scribed by Zhang, Xinmiao; Cai, Fang

Book ID: 118154549
Publisher: IEEE
Year: 2011
Weight: 624 KB
Volume: 0
Category: Article
ISBN: 1612848567
DOI: 10.1109/mwscas.2011.6026389

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