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[IEEE 2010 International Conference on Field Programmable Logic and Applications (FPL) - Milan, Italy (2010.08.31-2010.09.2)] 2010 International Conference on Field Programmable Logic and Applications - Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA

✍ Scribed by Lhairech-Lebreton, Ghizlane; Coussy, Philippe; Martin, Eric

Book ID: 118153086
Publisher: IEEE
Year: 2010
Weight: 546 KB
Volume: 0
Category: Article
ISBN: 1424478421
DOI: 10.1109/fpl.2010.94

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