[IEEE 2010 IEEE Symposium on VLSI Technology - Honolulu, HI, USA (2010.06.15-2010.06.17)] 2010 Symposium on VLSI Technology - A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

✍ Scribed by Basker, V. S.; Standaert, T.; Kawasaki, H.; Yeh, C.-C.; Maitra, K.; Yamashita, T.; Faltermeier, J.; Adhikari, H.; Jagannathan, H.; Wang, J.; Sunamura, H.; Kanakasabapathy, S.; Schmitz, S.; Cummings, J.; Inada, A.; Lin, C. -H.; Kulkarni, P.; Zhu, Y.; Kuss, J.; Yamamoto, T.; Kumar, A.; Wahl, J.; Yagishita, A.; Edge, L. F.; Kim, R. H.; Mclellan, E.; Holmes, S. J.; Johnson, R. C.; Levin, T.; Demarest, J.; Hane, M.; Takayanagi, M.; Colburn, M.; Paruchuri, V. K.; Miller, R. J.; Bu, H.; Doris, B.; McHerron, D.; Leobandung, E.; O'Neill, J.

• Book ID: 121193168
• Publisher: IEEE
• Year: 2010
• Weight: 973 KB
• Category: Article
• ISBN: 1424454514
• DOI: 10.1109/VLSIT.2010.5556135