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[IEEE 2009 International Conference on Field Programmable Logic and Applications (FPL) - Prague, Czech Republic (2009.08.31-2009.09.2)] 2009 International Conference on Field Programmable Logic and Applications - Clock gating architectures for FPGA power reduction

✍ Scribed by Huda, Safeen; Mallick, Muntasir; Anderson, Jason H.

Book ID: 121843542
Publisher: IEEE
Year: 2009
Weight: 620 KB
Category: Article
DOI: 10.1109/FPL.2009.5272538

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