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[IEEE 2009 IEEE International Solid-State Circuits Conference (ISSCC 2009) - San Francisco, CA (2009.02.8-2009.02.12)] 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers - A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes

✍ Scribed by Shiga, H.; Takashima, D.; Shiratake, S.; Hoya, K.; Miyakawa, T.; Ogiwara, R.; Fukuda, R.; Takizawa, R.; Hatsuda, K.; Matsuoka, F.; Nagadomi, Y.; Hashimoto, D.; Nishimura, H.; Hioka, T.; Doumae, S.; Shimizu, S.; Kawano, M.; Taguchi, T.; Watanabe, Y.; Fujii, S.; Ozaki, T.; Kanaya, H.; Kumura, Y.; Shimojo, Y.; Yamada, Y.; Minami, Y.; Shuto, S.; Yamakawa, K.; Yamazaki, S.; Kunishima, I.; Hamamoto, T.; Nitayama, A.; Furuyama, T.

Book ID: 120072638
Publisher: IEEE
Year: 2009
Weight: 629 KB
Category: Article
ISBN: 1424434580
DOI: 10.1109/ISSCC.2009.4977509

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