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[IEEE 2009 IEEE 13th Digital Signal Processing Workshop and 5th IEEE Signal Processing Education Workshop - Marco Island, FL, USA (2009.01.4-2009.01.7)] 2009 IEEE 13th Digital Signal Processing Workshop and 5th IEEE Signal Processing Education Workshop - High Speed DSP Block for FPGA Devices Using a Programmable Adder Graph

✍ Scribed by Howard, Charles D.; DeBrunner, Linda S.

Book ID: 127278148
Publisher: IEEE
Year: 2009
Weight: 191 KB
Category: Article
DOI: 10.1109/dsp.2009.4785973

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