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[IEEE 2008 35th International Symposium on Computer Architecture (ISCA) - Beijing, China (2008.06.21-2008.06.25)] 2008 International Symposium on Computer Architecture - MIRA: A Multi-layered On-Chip Interconnect Router Architecture

โœ Scribed by Park, Dongkook; Eachempati, Soumya; Das, Reetuparna; Mishra, Asit K.; Xie, Yuan; Vijaykrishnan, N.; Das, Chita R.

Book ID
115525645
Publisher
IEEE
Year
2008
Weight
472 KB
Volume
0
Category
Article
ISBN
0769531741

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[IEEE 2008 35th International Symposium
[IEEE 2008 35th International Symposium on Computer Architecture (ISCA) - Beijing, China (2008.06.21-2008.06.25)] 2008 International Symposium on Computer Architecture - MIRA: A Multi-layered On-Chip Interconnect Router Architecture
โœ Park, Dongkook; Eachempati, Soumya; Das, Reetuparna; Mishra, Asit K.; Xie, Yuan; ๐Ÿ“‚ Article ๐Ÿ“… 2008 ๐Ÿ› IEEE โš– 472 KB

Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron technology. However, almost all prior studies have focused on 2D NoC designs. Since three dimensional (3D) integration has em