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[IEEE 2007 International Semiconductor Device Research Symposium - College Park, MD, USA (2007.12.12-2007.12.14)] 2007 International Semiconductor Device Research Symposium - Vertical silicon-on-nothing FET: Threshold voltage calculation using compact capacitance model

✍ Scribed by Svilicic, Boris; Jovanovic, Vladimir; Suligoj, Tomislav

Book ID: 118154537
Publisher: IEEE
Year: 2007
Weight: 251 KB
Volume: 0
Category: Article
ISBN: 1424418925
DOI: 10.1109/isdrs.2007.4422545

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