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[IEEE 2007 IEEE International Symposium on Circuits and Systems - New Orleans, LA, USA (2007.05.27-2007.05.30)] 2007 IEEE International Symposium on Circuits and Systems - Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check Codes

✍ Scribed by Oh, Daesun; Parhi, Keshab K.

Book ID: 125845910
Publisher: IEEE
Year: 2007
Tongue: English
Weight: 280 KB
Category: Article
ISBN-13: 9781424409211
DOI: 10.1109/ISCAS.2007.378276

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