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[IEEE 2006 International Conference on Field Programmable Logic and Applications - Madrid, Spain (2006.08.28-2006.08.30)] 2006 International Conference on Field Programmable Logic and Applications - A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC Codes

✍ Scribed by Saunders, Paul; Fagan, Anthony

Book ID: 121316927
Publisher: IEEE
Year: 2006
Weight: 138 KB
Category: Article
ISBN-13: 9781424403127
DOI: 10.1109/FPL.2006.311328

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