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[IEEE 2002 IEEE International Symposium on Circuits and Systems - Phoenix-Scottsdale, AZ, USA (26-29 May 2002)] 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) - Evaluation on power reduction applying gated clock approaches

✍ Scribed by Palumbo, G.; Pappalardo, F.; Sannella, S.

Book ID: 118277841
Publisher: IEEE
Year: 2002
Weight: 249 KB
Volume: 4
Category: Article
ISBN-13: 9780780374485
DOI: 10.1109/iscas.2002.1010394

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