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[IEEE 1992 Bipolar/BiCMOS Circuits and Technology Meeting - Minneapolis, MN, USA (7-8 Oct. 1992)] Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting - A BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers using Wallace tree reduction architecture

✍ Scribed by Kuo, J.B.; Liao, H.J.; Chen, H.P.

Book ID: 125510380
Publisher: IEEE
Year: 1992
Weight: 367 KB
Category: Article
ISBN-13: 9780780307278
DOI: 10.1109/BIPOL.1992.274053

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