[IEEE 17th IEEE Symposium on Computer Arithmetic (ARITH'05) - Cape Cod, MA, USA (27-29 June 2005)] 17th IEEE Symposium on Computer Arithmetic (ARITH'05) - Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition

✍ Scribed by Bruguera, J.D.; Lang, T.

• Book ID: 118022507
• Publisher: IEEE
• Year: 2005
• Tongue: English
• Weight: 247 KB
• Volume: 0
• Category: Article
• ISBN-13: 9780769523668
• DOI: 10.1109/arith.2005.22

✦ Synopsis

Arith 2005 Reports On New Innovative Techniques In The Theory Of Arithmetic Performed In Computers And Details The Design Of New Arithmetic Units In State Of The Art Microprocessors And Embedded Processors. This Year's Technical Program Includes 34 Papers With Authors Representing 13 Countries. These Papers Cover State Of The Art Techniques For Computer Arithmetic That Are In Use Today Or In The Near Future. For Instance The Cell Processor's Spu Is Examined Which Will Be Used In Future Video Game Systems. Techniques For Performing Complex Arithmetic Functions Such As Inverse Tangent On Recently Released Microprocessors Are Explored. Advances Have Been Made In Basic Operations Such As Adder Design And In Dual Datapath Fused Multiply-adders. Arith 2005's Papers Provide A Spectrum Of All The Current Research In Computer Arithmetic Including Both Academic Research And Development In Industry.