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[IEEE 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07) - Berkeley, CA, USA (2007.03.12-2007.03.14)] 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07) - Gate-level modelling and verification of asynchronous circuits using CSPM and FDR

✍ Scribed by Josephs, Mark B.

Book ID: 126604198
Publisher: IEEE
Year: 2007
Tongue: English
Weight: 198 KB
Category: Article
ISBN-13: 9780769527710
ISSN: 1522-8681
DOI: 10.1109/ASYNC.2007.19

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