IC Mask Design: Essential Layout Techniques

✍ Scribed by Christopher Saint, Judy Saint

• Publisher: McGraw-Hill Professional
• Year: 2002
• Tongue: English
• Leaves: 481
• Edition: 1
• Category: Library

✦ Synopsis

Integrated Circuit Mask Design teaches integrated circuit (IC) processes, mask design techniques, and fundamental device concepts in everyday language. It develops ideas from the ground up, building complex concepts out of simple ones, constantly reinforcing what has been taught with examples, self-tests and sidebars covering the motivation behind the material covered.

✦ Table of Contents

Contents......Page 7
Introduction......Page 15
Acknowledgments......Page 17
Open Letter to Circuit Designers......Page 19
Opening Thoughts on Digital Layout......Page 23
Verifying the Circuitry Logic......Page 24
Compiling a Netlist......Page 25
Floorplanning......Page 29
Placement......Page 33
Routing......Page 35
Prefabricated Gate Array Chips......Page 40
Design Verification......Page 41
Physical Verification......Page 42
Library Management......Page 43
Summary and Flowchart......Page 44
Closure on Digital Layout......Page 45
Here’s What We’ve Learned......Page 46
Opening Thoughts on Standard Cell Techniques......Page 47
Grid-Based Systems......Page 48
Directional Layer Technique......Page 51
Input and Output Alignment......Page 54
Fixed Height, Variable Width......Page 56
Common N Well......Page 57
Half-Grid Cell Sizing......Page 59
Half Design Rule......Page 60
Routing Channels......Page 61
Standardized Input and Output Cells......Page 67
Using Standardization in Analog Mask Design......Page 68
Closure on Standard Cell Techniques......Page 69
Here’s What We’ve Learned......Page 70
Opening Thoughts on Analog Layout......Page 71
Difference of Scale......Page 72
Difference of Teamwork......Page 73
Difference of Constraints......Page 74
Three Key Questions......Page 75
Question 1: What does this circuit do?......Page 77
Question 2: How much current does it take?......Page 78
Question 2a: Where are the high and low current paths?......Page 80
Device Orientation......Page 81
Additional Questions......Page 86
Bipolar Analog......Page 87
Expectations of an Analog Mask Designer......Page 88
Here’s What We’ve Learned......Page 92
Appendix: Key Questions Discussion......Page 93
Opening Thoughts on Parasitics......Page 101
Parasitic Capacitance......Page 102
Wire Length......Page 103
Metal Selection......Page 104
Metal over Metal......Page 106
Calculating IR Drops......Page 108
Wiring Options......Page 110
Parasitic Inductance......Page 113
CMOS Transistor Example......Page 114
Bipolar Transistor Example......Page 115
Closure on Parasitics......Page 116
Here’s What We’ve Learned......Page 117
Opening Thoughts on Matching......Page 119
Importance of Layout......Page 120
Simple Matching......Page 122
Root Device Method......Page 125
Interdigitating Devices......Page 127
Dummy Devices......Page 130
Common Centroid......Page 131
Cross-Quading......Page 132
Symmetry......Page 135
Matching Signal Paths......Page 136
Device Size Choices......Page 139
Closure on Matching......Page 141
Rules of Matching......Page 142
Opening Thoughts on Noise Issues......Page 143
Noisy Neighbors......Page 144
Turn Down the Volume......Page 146
Rock Band Moves Inside Their House......Page 147
Call the Sheriff......Page 150
Move to a New Neighborhood......Page 151
Coaxial Shielding......Page 152
Differential Signals......Page 154
Decoupled Power Rails......Page 156
Stacked Power Rails......Page 157
Harmonic Interference......Page 158
Here’s What We’ve Learned......Page 161
Opening Thoughts on Floorplanning......Page 163
Primary Drivers of Floorplanning......Page 164
Pin-Driven Planning......Page 165
Block-Driven Planning......Page 171
Signal-Driven Planning......Page 174
Reshaping Blocks......Page 175
Leaving Enough Room......Page 177
Estimating with Existing Circuitry......Page 180
Closure on Floorplanning......Page 181
Here's What We've Learned......Page 182
General Techniques......Page 183
#1 Pick Five or Six Non-minimum Design Rules......Page 184
#3 Plenty of Wide Wiring and Vias......Page 187
#4 Don't Believe Your Circuit Designer......Page 189
#5 Use a Consistent Orientation......Page 190
#7 Keep Off the Blocks......Page 191
#9 If It Looks Nice, It Will Work......Page 192
#10 Learn Your Process......Page 193
#12 Spread Your Spinach around Your Dinner Plate......Page 194
#13 Copy and Rename Cells before Making Changes......Page 197
#14 Remember Your Hierarchy Level......Page 198
#15 Build-in Easy Metal Revisions......Page 199
#16 Draw Big Power Buses......Page 204
Closure on General Techniques......Page 206
Ancient Secrets of Mask Design......Page 207
Opening Thoughts on Packaging......Page 209
Bonding Methods......Page 210
Ultrasonic Wedge Bonding......Page 211
Ultrasonic Ball Bonding......Page 212
Flip Chip Technology......Page 213
Multi-Tier Packaging......Page 214
Overall Appearance......Page 215
45-Degree Rule......Page 216
Wire Length......Page 217
Pad Distribution......Page 218
Pad-Limited Design......Page 219
Core-Limited Design......Page 221
Final Die Size Calculations......Page 222
Filling Pad Gaps......Page 228
Closure on Packaging......Page 229
Here's What We've Learned......Page 230
Opening Thoughts on Verification......Page 231
Checking Software......Page 232
Design Rule Check (DRC)......Page 233
Layout Versus Schematic (LVS)......Page 242
Closure on Verification......Page 256
Here's What We've Learned......Page 257
Opening Thoughts on Data Formats......Page 259
Coordinating Resolutions......Page 260
Pattern Generation......Page 263
Know Your Grids......Page 264
Here's What We've Learned......Page 265
The New Job Assignment......Page 269
Bill Reasons His Floorplan......Page 277
Bill Thinks Through His Layout......Page 281
Ted Returns......Page 294
Bill Rethinks......Page 302
The Chip Is Assembled......Page 326
Packaging......Page 347
Appendix......Page 348
Introduction to Case Study 2......Page 363
"What Does the Circuit Do?"......Page 364
Bipolar Transistor Review......Page 367
Initial Overview......Page 368
Current Source......Page 371
Lower Pair......Page 373
Upper Quad......Page 377
Loads......Page 380
Bipolar Transistor Layout—Wrap-Around Technique......Page 384
Current Source......Page 387
Lower Pair......Page 392
Upper Quad......Page 397
Loads......Page 402
Analysis of Second Layout......Page 406
Third Layout......Page 407
Lower Pair......Page 408
Comparison of Case Study 1 and Case Study 2......Page 415
Beginnings......Page 417
The Four Engineers......Page 431
Outtakes......Page 433
Contact Us......Page 437
Suggested Readings and Resources......Page 439
Educational Programs......Page 441
A......Page 443
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C......Page 445
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Q......Page 458
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