How to make RISC-V Microcomputer using FPGA for programmer

✍ Scribed by Horie, Tetsuya

• Year: 2019
• Tongue: English
• Leaves: 283
• Category: Library

✦ Table of Contents

Preface
Required knowledge
Required device
If you already have an FPGA board
Operating System for development
This book chapters
Souce code in this book
RISC-V and tools to make RISC-V microcomputer
What is RISC-V
Background for RISC
Examples and current situation
What is RISC-V
RISC-V run on FPGA
What is Chisel
What is Scala
Introduction of FPGA
Install of development tools
Install of OpenJDK
Install of sbt
Install of Verilator
Install of Vivado
Install of FPGA board file.
Download of template of constraint file of FPGA.
Programing with Chisel
Creating project for Chisel
"Hello, World!" in Scala
Programming with Chisel
Generate a Verilog file from Chisel code
Programming the FPGA board with Vivado
Launch Vivado and create a Vivado project
Edit constraint file.
Connect FPGA board to PC
Synthesize and configuration of FPGA
Write program to configuration ROM. Load circute on booting FPGA.
About the cirucute that we programed
Combinational circuit
Electrical circuit and computer logic
Taxonomy of electric circuits
0 and 1, Low and High, it was decided by the designer
0 and 1, true and false, and computer operations, ie logical operations
Input Output and Bitwise operator
Bundle multiple signals(Vec)
In Scala, all operations are method calls
Number (UInt, SInt) and Reduction operation, Implicit type conversion in Scala
Conditional Assignment(Mux) and Structual Modeling, Bit concatenation(Cat)
Conditional Assignment(Mux)
Structual Modeling
Functional Module
Notes on Mux in Chisel
Bit concatenation(Cat)
Decoder(MuxCase)
Adder
Half Adder
Full Adder
4 bit adder
Scala as a hardware configuration script
Subtractor
Comparison of the numbers
Bit shifts
Multiplier
Recap of Chisel's operators
List of operators
Priority of operator
ALU
Sequential circuit
Latch and flip flop
SR Latch
D latch
D flip flop
Resetable flip flop
Flip flop with enable function
Register
Counting
Count up(1 digit sec clock)
Dynamic lighting (Clock)
Debounce (Stopwatch)
State machine (Kitchen timer)
Specifications of kitchen timer
UML state diagram
Implementation of kitchen timer
Serial to parallel conversion, Synchronizer
PS/2 keyboard (Synchronous serial communication)
UART (Asynchronous serial communication)
Implicit state
Color bar on VGA display
Wrap Verilog code in Chisel
BlackBox
Multi clock domain
Generate a clock
Generate VRAM, character ROM
Change the display module
Change CharVramWriter
Change top module
Introduction to RISC-V
Emulator
Install QEMU
Install the RISC-V toolchain
Assembler
Hello, world!
R of RISC means Reduced
Main memory and registers
Memory mapped I/O
Arithmetic operation
Bitwise logical operation
Shift operation
Relational operation
Conditional branching
Jump
Other operation
Linker script
Calling convention
Call stack
Machine code
Contents of executable file
Disassemble
Instruction form
C programming language
Hello, world!
Suppression of optimization
Stack pointer definition
Making RISC-V microcomputer
CPU is a state machine
Register
Program counter
Register file
Memory
Harvard architecture
Instruction memory
Data memory
Memory implementation
Decoder
Read register value
Generation of internal control signal
Add decoder to CPU core
Arithmetic logic unit(ALU)
Calculation of read/write address
Arithmetic operation, Bitwise logical operation, Shift operation, Relational operation
Conditional branching
Jump
Implement ALU on CPU core
Memory access
Write back to register
Program counter update
Memory mapped I/O
Lower clock frequency
Generate IP using Vivado
Create a low frequency clock domain
Make program initial data
Pipeline processor
Pipeline
Hazard
Change clock frequency
Open source RISC-V implementation
What is needed to complete a microcontroller
Rocket Chip
Freedom Platform
Customize Rocket Chip
Rocket Chip source code
TileLink
Add LED Module to Rocket Chip
Customize Freedom E300
Freedom FPGA Development Kit
Freedom E300 Class Structure
Create VGA device
Create Freedom FPGA
VGA screen output software
Create Configuration File of FPGA Board
Appendix
Third party license