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High throughput and low-latency implementation of bit-level systolic architecture for 1D and 2D digital filters

✍ Scribed by Mohanty, B.K.; Meher, P.K.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Cost-effective novel flexible cell-level

✍ Mohanty, B.K.; Meher, P.K. 📂 Article 📅 1996 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 339 KB

Bit-level systolic imlementation of 1D a

✍ Nayak, S.S. 📂 Article 📅 2005 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 561 KB

Area- and Power-Efficient Architecture f

✍ Mohanty, B. K.; Mahajan, A.; Meher, P. K. 📂 Article 📅 2012 🏛 Institute of Electrical and Electronics Engineers 🌐 English ⚖ 883 KB

Serial architectures for the implementat

✍ Sid-Ahmed, M.A. 📂 Article 📅 1990 🏛 IEEE ⚖ 393 KB