A study about the efficiency of formal h
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JosΓ© M. MendΔ±Μas; RomΓ‘n Hermida; Olga PeΓ±alba
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Article
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2002
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Elsevier Science
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English
β 643 KB
The use of a formal synthesis system is proposed as an efficient alternative for the formal verification of RT-level circuits obtained from algorithmic-level specifications by high-level synthesis (HLS) tools. The goal of the proposal is to recreate, within the formal synthesis system, any design pr