High Performance Multi-Channel High-Speed I/O Circuits

✍ Scribed by Taehyoun Oh, Ramesh Harjani (auth.)

Publisher: Springer-Verlag New York
Year: 2014
Tongue: English
Leaves: 91
Series: Analog Circuits and Signal Processing
Edition: 1
Category: Library

No coin nor oath required. For personal study only.

✦ Synopsis

This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures.

✦ Table of Contents

Front Matter....Pages i-x
Introduction....Pages 1-9
$$2\times 6$$ 2 × 6 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process....Pages 11-25
$$4 \times 12$$ 4 × 12 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process....Pages 27-46
Adaptive XTCR, AGC, and Adaptive DFE Loop....Pages 47-67
Research Summary and Contributions....Pages 69-71
Back Matter....Pages 73-89

✦ Subjects

Circuits and Systems; Electronics and Microelectronics, Instrumentation; Microwaves, RF and Optical Engineering

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