With the rapid growth in computing technology and the ever increasing needs of present and future computation-intensive applications, the past decade has witnessed the proliferation of high performance computing architectures and powerful parallel and distributed systems. In this special issue, the guest editors have put together some of the recent new developments and trends in this important area. The eleven selected papers in this special issue span a wide range of topics, including Systems-on-Chip (SoC) and Networks-on-Chip (NoC) architectures, embedded and reconfigurable computing architectures, circuit design methodology, high-performance interconnection architectures, and parallel and distributed computing systems.
As the density of transistors on a chip increases, the trend towards integrating more functionality onto a single chip has driven the emergence of Multiprocessor System on Chip (MPSoC). MPSoC is believed to gain a better performance with lower power consumption and suitable for many embedded system applications. While the number of processor cores on one chip is continuously increasing, the traditional bus-based architecture tends to create a communication bottleneck. As a result, NoC has emerged as a novel paradigm in MPSoC design for providing better structure, performance, and modularity.
The first four papers in this issue present the study of the problems falling into the four important research topics in NoCs: design space exploration, modeling and performance analysis, communication protocol design, and optical NoC architecture. The first paper by Liu et al. presents an NoC architecture design space exploration method, named Layer Interactive Building (LIB), for MPSoC architectures. Lee and Bagherzadeh present a semi-automated power estimation framework for power exploration at system level for NoC routers. Wang et al. present an adaptive and minimal routing scheme based on routing tables for mesh-based NoC architectures. The next paper by Zhang et al. introduces a promising optical NoC architecture, the wavelength routed optical networks (WRON), and studies the routing schemes of WRON and its variants.
Due to the high-performance they can offer, the cost saved, improved time-to-market, and improved flexibility and upgradability, reconfigurable computing systems are becoming increasingly attractive for many applications, respectively. The paper by Birk and Fiksman presents two new multi-context FPGA architectures based on local and centralized configuration-storage architectures and studies the configuration storage and reconfiguration overhead. The next paper by Lu and Liang addresses the energy consumption, execution efficiency, and speed issues of Java applications in a typical consumer mobile device environment and presents the design of a Java accelerator with a companion Java virtual machine.
With the increasing clock frequency, die size and the number of transistors, today's high performance VLSI design is challenged by high power consumption and synchronization problems. Compared to synchronous circuits, asynchronous circuits have the advantages of high performance, low noise, and robustness to parameters variations, but lack automatic synthesis and optimization tools. Ghavami and Pedram present a framework for performance driven synthesis of practical asynchronous circuits including choices under design parameter constraints.
Interconnection networks have been widely used in parallel processing, communication systems, and multiprocessor systems. The performance of a parallel computing system heavily depends on the effectiveness of the underlying interconnection network. The next two papers study the fault-tolerance capability of interconnection networks and parallel algorithm running on optical interconnections, respectively. The paper by Dong et al. addresses the fault-tolerant hamiltonicity of generalized honeycomb torus (GHT), an attractive alternative to torus. The following paper by He et al. studies the Cole's pipelined merge sort on the CREW PRAM and extends it to the Linear Array with Reconfigurable Pipelined Bus System model, an optical interconnection model.
Clusters have become increasingly popular as the powerful and cost-effective platforms for executing computationally large or data-intensive applications. Compared with conventional cluster computing systems, the grids used in grid computing tend to be more loosely coupled, heterogeneous, and geographically dispersed. The next two papers are focused on the research issues on cluster and grid computing. Fei et al. study the resource management problem in grid systems and present a load-balancing strategy and power-management policy based on a queuing analytical model. The paper by Zhu and Lu addresses the issue of security service for real-time applications and proposes a two-phase scheduling strategy which takes timing constraints and security needs into consideration.