Hardware Supply Chain Security: Threat Modelling, Emerging Attacks and Countermeasures

✍ Scribed by Basel Halak (editor)

• Publisher: Springer
• Year: 2021
• Tongue: English
• Leaves: 221
• Category: Library

✦ Synopsis

This book presents a new threat modelling approach that specifically targets the hardware supply chain, covering security risks throughout the lifecycle of an electronic system. The authors present a case study on a new type of security attack, which combines two forms of attack mechanisms from two different stages of the IC supply chain. More specifically, this attack targets the newly developed, light cipher (Ascon) and demonstrates how it can be broken easily, when its implementation is compromised with a hardware Trojan. This book also discusses emerging countermeasures, including anti-counterfeit design techniques for resources constrained devices and anomaly detection methods for embedded systems.

✦ Table of Contents

Preface
The Contents at Glance
Book Audience
Acknowledgments
Contents
About the Editor
Part I Threat Modelling of Hardware Supply Chain
1 CIST: A Threat Modelling Approach for Hardware Supply Chain Security
1.1 Introduction
1.1.1 Motivation
1.1.2 Chapter Summary
1.2 Background
1.2.1 Related work
1.2.2 Description of IC Production Process
1.2.3 Preliminaries
1.2.3.1 How to Develop a Secure System in a Nutshell
1.2.3.2 Attack Difficulty
1.2.3.3 Adversary Classification
1.3 CIST: A Hardware-Specific Threat Modelling Approach
1.4 Define: Definition of Security Properties
1.5 Model: Modelling the IC Supply Chain Security
1.6 Identification of Threats
1.6.1 Counterfeiting
1.6.2 Information Leakage
1.6.2.1 IP Piracy
1.6.2.2 Data Theft
1.6.3 Sabotage
1.6.3.1 Cyber-Physical Attacks
1.6.3.2 Rowhammer Attacks
1.6.3.3 CLKscrew Attacks
1.6.3.4 Attacks on IC Production
1.6.4 Tampering
1.6.4.1 Fault Injection Attacks
1.6.4.2 Software-on Hardware Attacks
1.6.4.3 Trojan Insertion
1.7 Mitigation Techniques
1.7.1 Countermeasures for Counterfeiting Attacks
1.7.1.1 Counterfeit Detection Techniques
1.7.1.2 Counterfeit Preventing Techniques
1.7.2 Countermeasures for Information Leakage Attacks
1.7.2.1 Countermeasure for IP Piracy
1.7.2.2 Countermeasures for Data Theft
1.7.3 Countermeasures for Sabotage Attacks
1.7.3.1 Countermeasures for Cyber-Physical Attacks
1.7.3.2 Countermeasures for Rowhammers Attack
1.7.3.3 Countermeasures for CLKscrew Attacks
1.7.4 Countermeasures for Tampering Attacks
1.7.4.1 Countermeasures for Hardware Trojan Insertion
1.7.4.2 Countermeasures for Fault Injection Attacks
1.8 Security Validation
1.8.1 Case Study 1: The Use of Obfuscation to Prevent PUF Modelling Attacks
1.8.2 Case Study 2: The Use of Logic Locking to Prevent IP Theft at the Manufacturing Stage
1.9 Conclusions
References
Part II Emerging Hardware-Based Security Attacks and Countermeasures
2 A Cube Attack on a Trojan-Compromised Hardware Implementation of Ascon
2.1 Introduction
2.1.1 Motivation
2.1.2 Chapter Summary
2.2 Background
2.2.1 Hardware Trojans
2.2.2 Ascon Algorithm
2.2.3 Cryptanalysis of Ascon
2.2.4 Cube Attack
2.3 Hardware Implementation of Ascon
2.3.1 Datapath
2.3.2 State Machine
2.3.3 Vulnerabilities of Hardware Implementation
2.4 Inserting Trojans in the Hardware Implementation of Ascon
2.4.1 Key-Bypass Trojan
2.4.2 Round-Reduction Trojan
2.5 Cube Attack on a Trojan-Compromised Hardware Implementation of Ascon
2.5.1 Attack Assumptions
2.5.2 Experimental Evaluation
2.5.3 Trojans Overhead
2.6 Related Attacks and Mitigation Techniques
2.6.1 Other Possible Attacks
2.6.2 Trojan Detection
2.6.3 Design Recommendations
2.7 Conclusions
References
3 Anti-counterfeiting Techniques for Resources-Constrained Devices
3.1 Introduction
3.2 Chapter Overview
3.3 Background
3.3.1 Rabin Cryptosystem
3.3.2 Related Work
3.4 Proposed Protocol
3.4.1 Proposed Solution
3.4.2 System Model
3.4.3 Attacker Model and Threat Assumptions
3.4.4 Main Design Aims
3.4.5 Proposed Mutual Authentication Protocol
3.4.5.1 Phase 1: Identification
3.4.5.2 Phase 2: Authentication
3.4.6 Data Retrieval Protocol
3.4.7 Recommendations for Security Level
3.5 Security Analysis
3.5.1 Security Requirements
3.5.1.1 Mutual Authentication
3.5.1.2 Confidentiality
3.5.1.3 Anonymity
3.5.1.4 Availability
3.5.1.5 Forward Security
3.5.1.6 Tag Unclonability
3.5.2 Analysis of the Proposed Protocol with Scyther
3.5.3 Verification of Security Requirements
3.5.4 Verification of Tag Unclonability
3.5.4.1 Test Vector Generation and Machine Learning
3.5.4.2 Model-Building Results
3.5.5 Comparison with Related Work
3.6 Design and Implementation
3.6.1 Tag Design
3.6.2 Hash Function (H)
3.6.3 PUF
3.6.4 Memories and Registers
3.7 Evaluation and Cost Analysis
3.7.1 Statistical Characteristics
3.7.1.1 PUF Performance Metrics
3.7.1.2 Performance of Single PUF Authentication
3.7.1.3 Performance of the Proposed Authentication Protocol
3.7.2 Cost Analysis
3.7.2.1 Area of the Tag
3.7.2.2 Comparison with Other Authentication Protocols
3.8 Conclusion
A.1 Appendix: Sample Code for the Proposed Protocol
References
Part III Anomaly Detection in Embedded Systems
4 Anomalous Behaviour in Embedded Systems
4.1 Introduction
4.2 Chapter Overview
4.3 Embedded Systems for Various Applications
4.4 Characteristics of Embedded Systems
4.5 Anomalies: Cause of Anomalous Behaviour
4.5.1 Type of Anomalies
4.6 Threats That Cause Anomalous Behaviour
4.6.1 Side-Channel Attacks
4.6.2 Software Attacks
4.6.3 Denial-of-Service (DoS) Attack
4.6.4 Control-Oriented and Data-Oriented Attacks
4.6.5 Fault Injection Attacks
4.7 Conclusion
References
5 Hardware Performance Counters (HPCs) for Anomaly Detection
5.1 Introduction
5.2 Chapter Overview
5.3 Type and Characteristics of Hardware Performance Counters (HPCs)
5.4 Hardware Performance Counters (HPCs) Operation Principles
5.4.1 Performance Monitoring Tools
5.5 Application of Hardware Performance Counters (HPCs)
5.5.1 Performance Evaluation
5.5.2 Workload Estimation
5.5.3 Detection of Malicious Activities
5.5.4 Anomaly Detection
5.6 Case Study 1: Anomaly Detection Using Support Vector Machine Method
5.6.1 Methodology
5.6.2 Implementation
5.6.3 Results and Discussion
5.6.4 Limitations
5.7 Case Study 2: Anomaly Detection Using Clustering-Based Method
5.7.1 Methodology
5.7.2 Implementation
5.7.3 Results and Discussion
5.7.4 Limitations
5.8 Conclusion
References
6 Anomaly Detection in an Embedded System
6.1 Introduction
6.2 Chapter Overview
6.3 Techniques for Anomaly Detection
6.4 A Case Study of Using HPCs for Early Detection and Prediction of Failure
6.4.1 Identification of Anomalous Behaviour
6.4.1.1 Experimental Setup
6.4.1.2 Comparison Between Two PMEs
6.4.1.3 Comparison on Various Sampling Interval
6.4.1.4 Comparison on Using Different Input Data
6.4.1.5 Correlation Between Errors and Failures
6.4.1.6 Normal vs Abnormal
6.4.1.7 Detection Interval
6.4.2 Early Detection and Prediction Algorithm
6.4.2.1 Predicting Potential Failure
6.4.2.2 One-Step Ahead Prediction
6.4.2.3 Measurement of Deviation and Anomaly Classification
6.4.2.4 Evaluation of Early Detection and Prediction Algorithm
6.4.3 Experimental Validation of the Detector
6.4.3.1 Design of the Detector
6.4.3.2 Simulation Results
6.4.4 Performance Analysis
6.4.5 Summary
6.5 Conclusion
References
Index