Hardware IP Security and Trust

✍ Scribed by Prabhat Mishra, Swarup Bhunia, Mark Tehranipoor (eds.)

• Publisher: Springer
• Year: 2017
• Tongue: English
• Leaves: 351
• Category: Library

✦ Synopsis

This book provides an overview of current Intellectual Property (IP) based System-on-Chip (SoC) design methodology and highlights how security of IP can be compromised at various stages in the overall SoC design-fabrication-deployment cycle. Readers will gain a comprehensive understanding of the security vulnerabilities of different types of IPs. This book would enable readers to overcome these vulnerabilities through an efficient combination of proactive countermeasures and design-for-security solutions, as well as a wide variety of IP security and trust assessment and validation techniques. This book serves as a single-source of reference for system designers and practitioners for designing secure, reliable and trustworthy SoCs.

✦ Table of Contents

Front Matter....Pages i-xii
Front Matter....Pages 1-1
Security and Trust Vulnerabilities in Third-Party IPs....Pages 3-14
Front Matter....Pages 15-15
Security Rule Check....Pages 17-36
Digital Circuit Vulnerabilities to Hardware Trojans....Pages 37-51
Code Coverage Analysis for IP Trust Verification....Pages 53-72
Analyzing Circuit Layout to Probing Attack....Pages 73-98
Testing of Side-Channel Leakage of Cryptographic Intellectual Properties: Metrics and Evaluations....Pages 99-131
Front Matter....Pages 133-133
Hardware Hardening Approaches Using Camouflaging, Encryption, and Obfuscation....Pages 135-163
A Novel Mutating Runtime Architecture for Embedding Multiple Countermeasures Against Side-Channel Attacks....Pages 165-184
Front Matter....Pages 185-185
Validation of IP Security and Trust....Pages 187-205
IP Trust Validation Using Proof-Carrying Hardware....Pages 207-225
Hardware Trust Verification....Pages 227-253
Verification and Trust for Unspecified IP Functionality....Pages 255-285
Verifying Security Properties in Modern SoCs Using Instruction-Level Abstractions....Pages 287-323
Test Generation for Detection of Malicious Parametric Variations....Pages 325-340
Front Matter....Pages 341-341
The Future of Trustworthy SoC Design....Pages 343-349
Back Matter....Pages 351-353