✦ LIBER ✦

Hardware-efficient systolic architecture for inversion and division in GF(2m)

✍ Scribed by Guo, J.-H.; Wang, C.-L.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

New systolic architectures for inversion

✍ Yan, Z.; Sarwate, D.V. 📂 Article 📅 2003 🏛 IEEE 🌐 English ⚖ 585 KB

Systolic architectures for inversion/div

✍ Nam-Yeun Kim; Kee-Young Yoo 📂 Article 📅 2003 🏛 Elsevier Science 🌐 English ⚖ 600 KB

A class of unidirectional bit serial sys

✍ Daneshbeh, A.K.; Hasan, M.A. 📂 Article 📅 2005 🏛 IEEE 🌐 English ⚖ 685 KB

Two systolic architectures for multiplic

✍ Tsai, W.C.; Wang, S.-J. 📂 Article 📅 2000 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 280 KB

Scalable and Systolic Architecture for C

✍ Chiou-Yng Lee; Jim-Min Lin; Che Wun Chiou 📂 Article 📅 2006 🏛 Springer Netherlands 🌐 English ⚖ 360 KB

New Bit-Parallel Systolic Architectures

✍ Chiou-Yng Lee; Che Wun Chiou 📂 Article 📅 2008 🏛 Springer US 🌐 English ⚖ 289 KB