✦ LIBER ✦

Hardware architecture for high-speed real-time dynamic programming applications

✍ Scribed by Matthews, B.; Elhanany, I.

Book ID: 117810010
Publisher: The Institution of Engineering and Technology
Year: 2008
Tongue: English
Weight: 228 KB
Volume: 2
Category: Article
ISSN: 1751-8601
DOI: 10.1049/iet-cdt:20070027

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

An optimum parallel architecture for hig

An optimum parallel architecture for high-speed real-time digital signal processing

✍ Lang, G.R.; Dharssi, M.; Longstaff, F.M.; Longstaff, P.S.; Metford, P.A.S.; Rimm 📂 Article 📅 1988 🏛 IEEE 🌐 English ⚖ 822 KB

An architecture and a dynamic scheduling

An architecture and a dynamic scheduling algorithm of grid for providing security for real-time data-intensive applications

✍ Mohd Rafiqul Islam; Mohd Toufiq Hasan; G. M. Ashaduzzaman 📂 Article 📅 2011 🏛 John Wiley and Sons 🌐 English ⚖ 261 KB

High speed lattice based VLSI architectu

High speed lattice based VLSI architecture of 2D discrete wavelet transform for real-time video signal processing

✍ Taegeun Park; Sunkyung Jung 📂 Article 📅 2003 🏛 IEEE 🌐 English ⚖ 415 KB

[IEEE Fifth International Workshop on Sy

[IEEE Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) - Banff, Alta., Canada (2005.07.20-2005.07.24)] Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) - High-speed serial links: design trends and challenges

✍ Stojanovic, V. 📂 Article 📅 2005 🏛 IEEE 🌐 English ⚖ 29 KB

[IEEE Fifth International Workshop on Sy

[IEEE Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) - Banff, Alta., Canada (2005.07.20-2005.07.24)] Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) - A review of current standards activities for high speed physical layers

✍ Palkert, T. 📂 Article 📅 2005 🏛 IEEE ⚖ 345 KB

[IEEE Comput. Soc 3rd IEEE International

[IEEE Comput. Soc 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications - Calgary, Alta., Canada (30 June-2 July 2003)] The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings. - Dynamic hardware-software partitioning on reconfigurable system-on-chip

✍ Waldeck, P.; Bergmann, N. 📂 Article 📅 2003 🏛 IEEE Comput. Soc 🌐 English ⚖ 236 KB

Papers from a summer 2003 workshop shed light on recent work in system-on-chip (SoC) design methodologies and physical design, low power SoCs, reconfigurable hardware, digital circuits, SoC applications, modeling issues in SoCs, and embedded processors. Other themes include analog and mixed signals,