This paper considers the use of data prefetching and an alternative mechanism, data forwarding, for reducing memory latency caused by interprocessor communication in cache coherent, shared memory multiprocessors. Data prefetching is accomplished by using a multiprocessor software pipelined algorithm
β¦ LIBER β¦
Hardware approaches to cache coherence in shared-memory multiprocessors. 2
β Scribed by Tomasevic, M.; Milutinovic, V.
- Book ID
- 117878234
- Publisher
- IEEE
- Year
- 1994
- Tongue
- English
- Weight
- 1015 KB
- Volume
- 14
- Category
- Article
- ISSN
- 0272-1732
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