Hardness-by-design approach for 0.15 /spl mu/m fully depleted CMOS/SOI digital logic devices with enhanced SEU/SET immunity

✍ Scribed by Makihara, A.; Midorikawa, M.; Yamaguchi, T.; Iide, Y.; Yokose, T.; Tsuchiya, Y.; Arimitsu, T.; Asai, H.; Shindou, H.; Kuboyama, S.; Matsuda, S.

• Book ID: 118049182
• Publisher: IEEE
• Year: 2005
• Tongue: English
• Weight: 310 KB
• Volume: 52
• Category: Article
• ISSN: 0018-9499
• DOI: 10.1109/tns.2005.860716