Handbook of Digital Techniques for High-Speed Design: Design Examples, Signaling and Memory Technologies, Fiber Optics, Modeling, and Simulation to Ensure Signal Integrity

✍ Scribed by Tom Granberg

• Publisher: Prentice Hall
• Year: 2004
• Tongue: English
• Leaves: 976
• Category: Library

✦ Synopsis

This practical handbook fills in gaps that other textbooks on high-speed design don't discuss, covering every aspect of high-speed board-level digital design. Several design examples at high Gigabit per second data rates are presented. Discusses highest-speed logic and interface families of devices, relevant applications, and device speeds versus how far signals transmit with good signal integrity. A quick-reference overview of each device family is also provided. High-speed design rules are presented for both engineering design and printed circuit board layout. Emphasizes designing high-speed backplanes, driving cabling, bus architecture and topology. Discusses IBIS and SPICE modeling, simulations, design processes, and over 30 design automation tools. Quantifies signal integrity using jitter and bit error rate measurements, eye diagrams, time-domain reflectometry and transmission. Details high-speed transmission line and parasitic effects, cabling, connectors, single-ended/differential terminations, lab test equipment, and intellectual property. Dedicated chapter on fiber optics and when to use.

✦ Table of Contents

Cover
Contents
Preface
How This Book Is Organized
This Textbook Was Written with Educational Institutions in Mind
University Courses for Which This Book Is Suitable
Solutions Manual Is Available
Cash for Identifying Textbook Errors
How This Book Was Prepared
Personal Acknowledgments
Technical Acknowledgments
Part 1 Introduction
Chapter 1 Trends in High-Speed Design
1.1 Everything Keeps Getting Faster and Faster!
1.2 Emerging Technologies and Industry Trends
1.3 Trends in Bus Architecture
1.4 High-Speed Design as an Offshoot from Microwave Theory
1.5 Background Disciplines Needed for High-Speed Design
1.6 Book Organization
1.7 Exercises
Chapter 2 ASICs, Backplane Configurations, and SerDes Technology
2.1 Application-Specific Integrated Circuits (ASICs)
2.2 Bus Configurations
2.3 SerDes Devices
2.4 Electrical Interconnects vs. Fiber Optics
2.5 Subtleties of Device Families
2.6 EDN Magazine’s Microprocessor Directory
2.7 Exercises
Chapter 3 A Few Basics on Signal Integrity
3.1 Transmission Lines and Termination
3.2 Important High-Speed Concepts
3.3 High-Frequency Effects: Skin Effect, Crowding Effect, Return Path Resistance, and Frequency-Dependent Dielectric Loss
3.4 Jitter Measurements Using Eye Patterns
3.5 BER Testing
3.6 Exercises
Part 2 Signaling Technologies and Devices
Chapter 4 Gunning Transceiver Logic (GTL, GTLP, GTL+, AGTL+)
4.1 Evolution from Backplane Transceiver Logic (BTL)
4.2 Gunning Transceiver Logic (GTL)
4.3 Gunning Transceiver Logic Plus (GTLP)
4.4 Intel’s AGTL+ and GTL+
4.5 GTLP/GTL/GTL+/AGTL+ Summary
4.6 Exercises
Chapter 5 Low Voltage Differential Signaling (LVDS)
5.1 Introduction to LVDS
5.2 Comparison of LVDS to Other Signaling Technologies Using Design Examples
5.3 Summary of LVDS Features and Applications
5.4 Exercises
Chapter 6 Bus LVDS (BLVDS), LVDS Multipoint (LVDM), and Multipoint LVDS (M-LVDS)
6.1 Justification for Enhanced Versions of LVDS
6.2 Bus LVDS (BLVDS)
6.3 LVDS Multipoint (LVDM)
6.4 Multipoint LVDS (M-LVDS)
6.5 Selecting BLVDS, BLVM, and M-LVDS Devices
6.6 Exercises
Chapter 7 High-Speed Transceiver Logic (HSTL) and Stub-Series Terminated Logic (SSTL)
7.1 High-Speed Transceiver Logic (HSTL)
7.2 Stub-Series Terminated Logic (SSTL)
7.3 Exercises
Chapter 8 Emitter Coupled Logic (ECL, PECL, LVPECL, ECLinPS Lite and Plus, SiGe, ECL Pro, GigaPro and GigaComm)
8.1 A Fast Technology—Edge Rates of 20 ps at 12 Gbps!
8.2 Basic Device Operation
8.3 The Two Major ECL Standards — 10K and 100K
8.4 Single-Ended and Differential Signaling
8.5 Component Nomenclature
8.6 The ECL Families and Their Characteristics
8.7 Summary of the ECL Families
8.8 Exercises
Chapter 9 Current-Mode Logic (CML)
9.1 CML Overview
9.2 CML Output Structure
9.3 CML Input Structure
9.4 ac- and dc-Coupled CML Circuits
9.5 XAUI Interface Standard
9.6 CML Design Considerations
9.7 How CML and ECL Differ
9.8 SuperLite CML and GigaPro™ CML
9.9 Vendor-Specific CML Examples
9.10 Summary of Current-Mode Logic (CML)
9.11 Exercises
Chapter 10 FPGAs—11.1 Gbps RocketIOs and HardCopy Devices
10.1 Industry Trends
10.2 Altera FPGAs and CPLDs
10.3 Xilinx FPGAs and CPLDs
10.4 Exercises
Chapter 11 Fiber-Optic Components
11.1 Getting On Board with Optics
11.2 Comparison of Copper and Fiber Transmission Media
11.3 Application Space for High-Speed Optical Data Link Modules
11.4 Using Fiber for the Short Haul
11.5 The 10 Gbps X-Modules
11.6 PAROLI 2 Parallel Optical Link Modules and Backplane Optical Interconnects
11.7 Dense-Wavelength-Division Multiplexing (DWDM)
11.8 Trends in the Application of Fiber Optics
11.9 Optical Cable Applications
11.10 Optical Internetworking Forum (OIF)
11.11 Fiber-Optic Connectors
11.12 Laser Safety
11.13 Vendors and Organizations for Fiber-Optic Components
11.14 Exercises
Chapter 12 High-Speed Interconnects and Cabling
12.1 SiliconPipe’s 12.8 GHz to 40 GHz Interconnect Solutions
12.2 High-Speed Connectors
12.3 High-Speed Cabling
12.4 Cables and Connectors for LVDS
12.5 Exercises
Part 3 High-Speed Memory and Memory Interfaces
Chapter 13 Memory Device Overview and Memory Signaling Technologies
13.1 Overview and Trends
13.2 A Quick Review of Memory Basics
13.3 Memory Signaling Technologies
13.4 Design Considerations in Use of Memory
13.5 Summary of Memory Devices and Terminology
13.6 Exercises
Chapter 14 Double Data Rate SDRAM (DDR, DDR2) and SPICE Simulation
14.1 DDR (Double Data Rate) SDRAM
14.2 DDR2 (Double Data Rate 2, DDR-II) SDRAM
14.3 SPICE/IBIS Simulation of DDR-II SDRAM
14.4 Exercises
Chapter 15 GDDR3, ZBT, FCRAM, SigmaRAM, RLDRAM, DDR SRAM, Flash, FeRAM, and MRAM
15.1 Graphics Double Data Rate SDRAM (GDDR, GDDR2, GDDR3)
15.2 ZBT, NoBL, ZeroSB, and NtRAM SRAM
15.3 FCRAM (Fast Cycle RAM)
15.4 SigmaRAM (ΣRAM)
15.5 RLDRAM (Reduced Latency DRAM)
15.6 DDR SRAM (Double Data Rate SRAM — DDR, DDRII SRAM)
15.7 Flash Memory
15.8 FeRAM (Ferroelectric RAM) and MRAM (Magnetoresistive RAM)
15.9 Memory Selection Guide
15.10 Exercises
Chapter 16 Quad Data Rate (QDR, QDRII) SRAM
16.1 Introduction to QDR
16.2 QDR SRAM Clocking Scheme
16.3 Comparison of QDR with QDRII
16.4 Exercises
Chapter 17 Direct Rambus DRAM (DRDRAM)
17.1 Direct Rambus DRAM™ (DRDRAM, RDRAM)
17.2 Long-Channel Design
17.3 Exercises
Chapter 18 Xtreme Data Rate (XDR) DRAM, FlexPhase and ODR
18.1 Introduction to XDR
18.2 XDR Physical Layer
18.3 XDR Logical Layer
18.4 Applications
18.5 Exercises
Part 4 Modeling, Simulation, and EDA Tools
Chapter 19 Differential and Mixed-Mode S-Parameters
19.1 S-Parameters Bridge the Gap Between Chips and Systems
19.2 The Rationale for Using S-Parameters
19.3 Single-Ended S-Parameters
19.4 Differential and Mixed-Mode S-Parameters
19.5 Calibration
19.6 Exercises
Chapter 20 Time Domain Reflectometry (TDR), Time Domain Transmission (TDT), and VNAs
20.1 Time Domain Reflectometry (TDR)
20.2 Time Domain Transmission (TDT)
20.3 TDR and TDT Simulations for a Loaded BLVDS Backplane
20.4 Vector Network Analyzer (VNA)
20.5 Exercises
Chapter 21 Modeling with IBIS
21.1 An Introduction to IBIS (I/O Buffer Information Specification) Modeling
21.2 Example of an IBIS Model
21.3 Exercises
Chapter 22 Mentor Graphics — EDA Tools for High-Speed Design, Simulation, Verification, and Layout
22.1 Overview of Mentor Graphics High-Speed Tools
22.2 ICX
22.3 Tau
22.4 HyperLynx
22.5 Mentor Graphics Field Solvers Used in ICX and HyperLynx
22.6 The Expedition Series and Design Flow
22.7 Signal Integrity and Timing Models
22.8 Use the Right Models for Simulation of Multigigabit Channels
22.9 Exercises
Part 5 Design Concepts and Examples
Chapter 23 Advances in Design, Modeling, Simulation, and Measurement Validation of High-Performance Board-to-Board 5-to-10 Gbps Interconnects
23.1 Introduction
23.2 Modeling Methodology
23.3 Simulation
23.4 Measurement
23.5 Measurement Accuracy Issues
23.6 Frequency Domain Measurement
23.7 Validation of Material Parameters
23.8 Stripline Measurements
23.9 Stripline Results
23.10 Calculation Methods and Validation
23.11 Conclusions
23.12 Exercises
Appendix 23.A: Generalized N-Port, Mixed-Mode S-Parameters
23.A.1 Why Do We Care?
23.A.2 Development of N-Port, Mixed-Mode S-Parameters
Chapter 24 IBIS Modeling and Simulation of High-Speed Fiber-Optic Transceivers
24.1 Introduction
24.2 IBIS Models for High-Speed Fiber-Optic Transceivers
24.3 The Electrical Board Description (EBD) File
24.4 Verification of IBIS Models
24.5 IBIS Models in “Real-World” Circuits
24.6 Signal Integrity Case Study
24.7 Summary
24.8 Exercises
Chapter 25 Designing with LVDS
25.1 Layer Stack-Up and PCB Design
25.2 PCB Board Layout Tips
25.3 LVDS Configurations
25.4 Failsafe Biasing of LVDS
25.5 Eye Pattern Test Circuit
25.6 BER Test Circuit
25.7 Exercises
Chapter 26 Designing to 10 Gbps Using SerDes Transceivers, Serializers, and Deserializers
26.1 Introduction and the DS92LV16 (2.56 Gbps)
26.2 Bus LVDS SerDes Architecture
26.3 Bus Topologies/Applications
26.4 Backplanes
26.5 PCB Recommendations
26.6 Cables and Connectors
26.7 Power and Ground
26.8 Clocking
26.9 Inputs and Outputs
26.10 Evaluating the DS92LV16
26.11 Loopback Testing
26.12 Lock to Random Data vs. SYNC Patterns
26.13 Interconnect Jitter Margin
26.14 Troubleshooting
26.15 Quad 2.5 Gbps (10 Gbps) Serializer/Deserializer (SerDes)
26.16 Eight-Channel 10:1 Serializer for 5.28 Mbps
26.17 Exercises
Chapter 27 WarpLink SerDes System Design Example
27.1 WarpLink Design Overview
27.2 Introduction
27.3 Detailed Design Descriptions
27.4 WarpLink Signal Integrity HSPICE Simulations
27.5 Descriptions of Passive Signal Integrity Measurements
27.6 Passive Measurement Results
27.7 Active Measurement Results
27.8 Summary and Conclusions
27.9 Exercises
Part 6 Emerging Protocols and Technologies
Chapter 28 Electrical Optical Circuit Board (EOCB)
28.1 The Photonic PCB Industry and Development Programs
28.2 Optoelectronic Printed Circuits Based on HDI-Microvia Technology
28.3 Photonics and Waveguides
28.4 Conclusion
28.5 Exercises
Chapter 29 RapidIO
29.1 RapidIO: The Interconnect Architecture for High-Performance Embedded Systems
29.2 RapidIO Is Now an International Standard
29.3 Embedded System Development
29.4 RapidIO Protocol Overview
29.5 Physical Interface
29.6 Maintenance and Error Management
29.7 Performance
29.8 Summary
29.9 Exercises
Chapter 30 PCI Express and ExpressCard
30.1 PCI Express as Next-Generation I/O
30.2 PCI Express Architecture Overview
30.3 PCI Express Architecture
30.4 Development Timeline
30.5 Summary
30.6 Exercises
Part 7 Lab and Test Instrumentation
Chapter 31 Electrical and Optical Test Equipment
31.1 Oscilloscopes
31.2 Bit Error Ratio Testers (BERTs)
31.3 Pulse Generators
31.4 Jitter Analyzers
31.5 Logic Analyzers
31.6 Characterizing Optical Systems
31.7 Test Equipment Specifications
31.8 Exercises
Acronyms
References
About the Author
Index
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