Abstract
A practical and unique hardware architecture for video bitstream source decoding and video postprocessing of a Moving Pictures Expert Group (MPEG‐2)‐based high‐definition television (HDTV) compressed bitstream has been implemented to impose minimal limitations on the video source coding algorithm. The Grand Alliance (GA) MPEG‐2‐based HDTV codec achieves a high degree of source and channel coding efficiency while preserving the delivery of high‐resoultion picture quality in a variety of video input and output formats in bandwidth‐limited channels. The video source decoder hardware architecture necessary to achieve the data decoding and ensuing video postprocessing poses numerous technologic challenges to the system designer, who must tradeoff minimizing codec constraints with the eventual commercialization of a video decoder for a consumer television receiver product. The powerful and flexible coding algorithm necessary to satisfy the HDTV picture quality and transmission channel bandwidth limitation requirements results in an encoder‐output bitstream that necessitates high throughout decoding. Although the transmitted bitstream is of constant rate due to rate buffering, bistreams internal to the codec are both peaky and bursty. An intelligent distributive parallel processing decoding architecture has been developed to dynamically partition the MPEG‐2 bitstream into a number of decodable subset bitstreams, while placing minimal constraints on the encoding algorithm. This architecture allows for high‐speed, efficient decoding of the bitstream, and can be a prelude to the development of a cost‐effective consumer product. Further architecture refinements can be explored, including implementation in VLSI.