We report herein how adding a monolayer of small ( % 2.5 nm diameter) Au nanoparticles (NPs) on top of an approximately 5-nm-thick insulating layer significantly enhances electronic current transport through the insulator. The insulating film is sandwiched between Au and Al or Si (degenerate) electrodes to give the following sandwich configuration: Au//Au NP monolayer/5-nm-thick insulating layer//Al or Si. Enhancement is found both with hard inorganic (SiO 2 ) and with soft organic insulators (lipid bilayers stabilized with bacteriorhodopsin (bR)).
Citrate-stabilized Au NPs ( % 2.5 nm diameter, unless stated otherwise) were synthesized as described elsewhere. [1] As a model insulating layer, we prepared SiO 2 layers on the surface of conducting, degenerate (100) n-Si substrates (%10 ร3 W cm). The Si wafers with native oxide layer (%1.8 nm) were first cleaned with organic solvents, then an oxide layer of controlled thickness was grown on top of them by plasma-assisted oxidation. The oxide-layer thickness was determined by ellipsometry. Unless otherwise stated, we used oxide layers with a thickness of (5.4 AE 0.5) nm. These samples were then used in both test and control junctions. The oxide layer was modified with (3-aminopropyl)trimethoxysilane (APTMS) [1a] to assemble the Au NPs (from a suspension with pH 5) on the oxide by binding them to the exposed APTMS amino groups. [2] After formation of a saturated Au NP monolayer (incubation time > 6 h), the NP-covered surface was treated with 20 mm aqueous cysteamine for 30 min to passivate the surface of the colloids. The junctions were prepared by depositing Au on top of the NP-covered surface. This deposition was done by floating preformed Au pads (60 nm thick, 0.5 mm diameter, 2 10 ร3 cm 2 area) onto the Au NP-covered surface in a nondestructive manner, using the "lift-off, float-on" technique (LOFO). [3] For control experiments we also evaporated Au onto the NP-covered surface. We constructed control junctions of the type Au pad// APTMS-SiO 2 ( % 5 nm)//Si in a similar manner.
Current-voltage (I-V) measurements were performed in a class 10 000 clean room at 293 K and 40 % relative humidity (RH). I-V characteristics were measured using a W needle connected to a micromanipulator to contact the Au pad-an InGa drop on the Au pad minimizes mechanical (pressure) damage to the film-and an HP 4155 semiconductor parameter analyzer. All I-V measurements were performed in the dark, unless noted otherwise. As shown in curve 1 of Figure 1, in the absence of the NP layer, the current that we measured through the approximately 5-nm-thick inorganic insulating layers is within the noise level ( % 100 pA). Adding the NP film changes this situation; typical currents through the Au pad//cysteamine/Au NP monolayer/APTMS-SiO 2 ( % 5 nm)// Si junctions were 0.3-2 nA at 1 V applied bias, as shown in curve 2 of Figure 1.
This result immediately suggested that the Au NPs are in direct contact with the Si substrate via pinholes or cracks in the oxide film. It therefore became important to investigate the topography of the oxide surface. Figure 2 (top) shows a typical tapping-mode AFM map of the Si/SiO 2 layer, which gives an average root-mean-square (rms) roughness of 0.10 nm, nearly identical to the roughness that we measured for the native oxide surface of Si. This result indicates that the as-grown SiO 2 layers form in a homogeneous fashion on the Si substrate. Figure 2 (middle) shows an AFM image of a densely packed monolayer of Au NPs on the APTMSmodified Si/SiO 2 surface. This AFM image is a tip-sample [*] Dr.