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Gated clock routing for low-power microprocessor design

โœ Scribed by Jaewon Oh; Pedram, M.


Book ID
119778783
Publisher
IEEE
Year
2001
Tongue
English
Weight
212 KB
Volume
20
Category
Article
ISSN
0278-0070

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Power-Aware Testing and Test Strategies
โœ Girard, Patrick; Nicolici, Nicola; Wen, Xiaoqing ๐Ÿ“‚ Article ๐Ÿ“… 2009 ๐Ÿ› Springer US ๐ŸŒ English โš– 676 KB

Managing the power consumption of circuits and systems is now considered one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as dynamic voltage scaling, clock gating or power gating techniques, are used today to control the power dissipati