Gate-source-drain architecture impact on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors

✍ Scribed by Jeamsaksiri, W.; Jurczak, M.; Grau, L.; Linten, D.; Augendre, E.; De Potter, M.; Rooyackers, R.; Wambacq, P.; Badenes, G.

• Book ID: 114617024
• Publisher: IEEE
• Year: 2003
• Tongue: English
• Weight: 684 KB
• Volume: 50
• Category: Article
• ISSN: 0018-9383
• DOI: 10.1109/ted.2003.810478