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Gate Capacitance Reduction Due to the Inversion Layer in High- /Metal Gate Stacks Within a Subnanometer EOT Regime
✍ Scribed by Iijima, R.; Edge, L.F.; Ariyoshi, K.; Bruley, J.; Paruchuri, V.; Takayanagi, M.
- Book ID
- 114620380
- Publisher
- IEEE
- Year
- 2011
- Tongue
- English
- Weight
- 405 KB
- Volume
- 58
- Category
- Article
- ISSN
- 0018-9383
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