β Scribed by M.J. Shute
No coin nor oath required. For personal study only.
This paper describes a number of aspects concerned with building the largest single chip computers possible, namely ones which occupy an entire wafer of semiconductor. The techniques for achieving this are grouped under the collective name of wafer scale integration, and have tended to be presented only at microelectronics conferences, and workshops. This is a pity since there is much that the functional programmer and the microelectronics designer have in common, and can learn from one another. Workers developing applicative languages and their environments can specify what facilities are required of computers, and hence what is expedient for implementation. The microelectronics designer can point out what structures and facilities are practical, and hence which structures are readily supported.
This paper describes those parts of wafer scale integration which have repercussions on functional programming and computer architecture design. It ties together those areas of computer science which are significant to microelectronics, such as the use of array and tree structures, and the novel use of cellular automata to configure fault free multiprocessor systems. It notes the compromises which have been made on the FFPM, Wasp, Zapp and Cobweb projects between elegant software support, and practical wafer scale hardware design. Lastly, it highlights those areas of research which can be usefully addressed by both communities in the future.
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## Abstract With recent advances in VLSI technology, WaferβScale Integration implementation is becoming realistic, wherein massively parallel multiprocessors are implemented on a single wafer. As a result of this technique, the connections among VLSI become unnecessary and a highβspeed, highβdensit