✦ LIBER ✦

FPGA implementation of digital filters for nuclear detectors

✍ Scribed by D. Alberto; E. Falletti; L. Ferrero; R. Garello; M. Greco; M. Maggiora

Publisher: Elsevier Science
Year: 2009
Tongue: English
Weight: 482 KB
Volume: 611
Category: Article
ISSN: 0168-9002
DOI: 10.1016/j.nima.2009.09.049

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

FPGA Implementation of Digital Filters S

FPGA Implementation of Digital Filters Synthesized Using the FRM Technique

✍ Yong Ching Lim; Ya Jun Yu; Huan Qun Zheng; Say Wei Foo 📂 Article 📅 2003 🏛 Springer 🌐 English ⚖ 86 KB

Systolic implementation of digital filte

Systolic implementation of digital filters

✍ S. Sunder; F. El-Guibaly; A. Antoniou 📂 Article 📅 1992 🏛 Springer US 🌐 English ⚖ 685 KB

Block implementation of two-dimensional

Block implementation of two-dimensional digital filters

✍ Sanjit K. Mitra; R. Gnanasekaran 📂 Article 📅 1983 🏛 Elsevier Science 🌐 English ⚖ 947 KB

A novel principle known as block transformation is developed for the block implementation of two-dimensional (2-D) digital filters. It employs the one-dimensional (1 -D) block implementation concept forwarded by Burrus (7) as a basic tool. Using this block transformation principle three distinctform

An efficient serial distributed arithmet

An efficient serial distributed arithmetic algorithm for FPGA implementation of digital up conversion

✍ T. Salim; J. Devlin; J. Whittington; M. I. Bhatti 📂 Article 📅 2005 🏛 John Wiley and Sons 🌐 English ⚖ 334 KB

Modified wave digital filters for improv

Modified wave digital filters for improved implementation by commercial digital signal processors

✍ Alfred Fettweis 📂 Article 📅 1989 🏛 Elsevier Science 🌐 English ⚖ 947 KB

FPGA implementation of self organizing m

FPGA implementation of self organizing map with digital phase locked loops

✍ Hiroomi Hikawa 📂 Article 📅 2005 🏛 Elsevier Science 🌐 English ⚖ 249 KB

The self-organizing map (SOM) has found applicability in a wide range of application areas. Recently new SOM hardware with phase modulated pulse signal and digital phase-locked loops (DPLLs) has been proposed (Hikawa, 2005). The system uses the DPLL as a computing element since the operation of the