FPGA EDA: Design Principles and Implementation

✍ Scribed by Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipović, Zhufei Chu

• Publisher: Springer
• Year: 2024
• Tongue: English
• Leaves: 229
• Edition: 1st ed. 2024
• Category: Library

✦ Synopsis

This book focuses on FPGA EDA tools, the very foundation of FPGA technology. Instead of illustrating how to use them, this book dives into the tools themselves, revealing how these tools are being designed and how they may improve. Unlike other semiconductors, FPGA has a distinctive two-stage EDA system: chip design EDA and application design EDA.State-of-the-art algorithms, data models and design methodologies/standards are the main concerns of this book, and these will be very helpful for FPGA EDA engineers and researchers to obtain a bird’s eye view of this complicated knowledge system. In the chip design EDA part, full-custom and semicustom methodologies bring up ASIC-like EDA tools, and in the application design EDA side, typical topics including high-level synthesis, logic synthesis, physical implementation, bitstream configuration, etc., are well discussed.

✦ Table of Contents

Foreword
Preface
Contents
Part I Introduction
1 Introduction
1.1 FPGA Hardware Brief Introduction
1.1.1 FPGA Concept
1.1.2 FPGA Hardware Evolution
1.1.3 FPGA Compares With Other Architectures
1.2 FPGA EDA Brief Introduction
1.2.1 FPGA EDA Concept
1.2.2 FPGA Chip Design EDA
1.2.3 FPGA Application Design EDA
References
Part II FPGA Data Modeling
2 Device (Chip Design) Modeling
2.1 Device Description Levels
2.1.1 Abstract Levels
2.1.2 Reuse Levels
2.2 Device Model Classifications
2.2.1 Primary Class
2.2.2 Metric Class
2.2.3 Guidance Class
2.3 Device Model Implementations
2.3.1 Logic Resource Structure Model
2.3.2 Configuration Bit Structure Model
2.3.3 Power Model
2.3.4 Performance (Timing) Model
2.3.5 Area Model
2.3.6 Packing/Placement Guidance Model
2.3.7 Routing Guidance Model
2.3.8 Bitstream Generation Guidance Model
References
3 Design (Application Design) Modeling
3.1 Design Description Levels
3.1.1 Abstract Levels
3.1.2 Reuse Levels
3.2 Design Model Classifications
3.2.1 Primary Class
3.2.2 Constraint Class
3.2.3 Report Class
3.3 Design Model Implementations
3.3.1 Logic Resource Structure Model
3.3.2 Configuration Bit Structure Model
3.3.3 Constraint Model
3.3.4 Report Model
References
Part III FPGA Metric Analysis
4 Power Analysis
4.1 Overview
4.2 Power Analysis Techniques
4.3 Summary and Trends
References
5 Performance (Timing) Analysis
5.1 Overview
5.2 Timing Analysis Techniques
5.3 Summary and Trends
References
6 Area Analysis
6.1 Overview
6.2 Area Analysis Techniques
6.3 Summary and Trends
References
Part IV FPGA Chip Design EDA
7 Semi-custom EDA
7.1 Overview
7.2 Extended Architecture Description Language
7.2.1 Circuit Modeling
7.2.2 Physical Mode Modeling
7.2.3 Configuration Protocol
7.3 Netlist Generator
7.4 Testbench Generator
7.5 Showcase
7.5.1 Methodologies
7.5.2 Performance Evaluation
7.6 Summary and Trends
References
Part V FPGA Application Design EDA
8 High-Level Synthesis
8.1 Overview
8.1.1 From Software Program to Intermediate Representation
8.1.2 From Intermediate Representation to Hardware Design
8.2 Datapath Scheduling
8.2.1 Unconstrained Scheduling
8.2.2 Constrained Scheduling
8.2.3 Timing Optimizations
8.2.4 Resource Binding and Sharing
8.3 Extracting Parallelism Through HLS Scheduling
8.3.1 SDC-Based Modulo Scheduling
8.3.2 Polyhedral Analysis and Optimization
8.3.3 Dynamic Scheduling
8.4 Current Status and Outlook
8.4.1 HLS Frameworks
8.4.2 HLS Code Restructuring and Annotations
8.4.3 Design Space Exploration
8.4.4 Functional and Formal Verification in HLS
8.4.5 Frequency Estimates in HLS
References
9 Logic Synthesis
9.1 Overview
9.2 Fundamentals of Boolean Logic
9.2.1 Boolean Algebra
9.2.2 Functional Representation
9.2.3 Directed-Acyclic-Graph (DAGs) Boolean Network
9.3 Logic Optimization
9.3.1 Functional Methodologies
9.3.2 DAG-Aware Logic Optimization
9.3.3 Exact Logic Optimization
9.3.4 Exact Synthesis Algorithm Flow
9.3.5 SAT-Based Encoding
9.3.6 Sequential Logic Optimization
9.3.7 Advanced Logic Optimization Techniques
9.4 Technology Mapping
9.4.1 Flow-Based and Cut-Based LUT Mapping
9.4.2 Cut-Less LUT Mapping
9.5 AI in Logic Synthesis
9.6 Summary and Trends
References
10 Physical Implementation
10.1 Packing
10.1.1 Overview
10.1.2 Seed-Based Packing Algorithms
10.1.3 Partition-Based Packing Algorithms
10.1.4 Summary and Trends
10.2 Placement
10.2.1 Overview
10.2.2 Annealing Placement Algorithms
10.2.3 Analytical Placement Algorithms
10.2.4 Summary and Trends
10.3 Routing
10.3.1 Overview
10.3.2 Negotiation-Based Routing Algorithms
10.3.3 Summary and Trends
References
11 Bitstream Configuration
11.1 Bitsream Generation
11.1.1 Overview
11.1.2 Mode-Based Technique
11.2 Bitsream Compression
11.2.1 Overview
11.2.2 Non-entropy Encoding
11.2.3 Entropy Encoding
11.3 Bitsream Encryption
11.3.1 Overview
11.3.2 AES-Based Technique
11.4 Bitstream Programming
11.4.1 Overview
11.4.2 JTAG-Based Technique
References
Part VI Summary and Outlook
12 Summary and Outlook
12.1 FPGA EDA's Crossroads
12.2 Our Book's Future Works