Fourier-transform analysis of inset dielectric guide with a conductor cover

✍ Scribed by Jong K. Park; Hyo J. Eom

• Book ID: 101270962
• Publisher: John Wiley and Sons
• Year: 1997
• Tongue: English
• Weight: 156 KB
• Volume: 14
• Category: Article
• ISSN: 0895-2477
• DOI: 10.1002/(sici)1098-2760(19970420)14:6<324::aid-mop5>3.0.co;2-k

✦ Synopsis

with a 15-ps fall time is compressed to one with a 7.2-ps fall time. In this simulation, the NLTL incorporates 42 diodes at w x 22.3-m spacings along a 90-⍀ CPW transmission line 8, 9 . These diodes have a series resistance, zero-bias capacitance, and built-in potential of 2.57 ⍀, 50 fF, and 0.8 V, respectively. Our FDTD simulation result is in close agreement with the SPICE result, in which a fall time of 6.9 ps is obtained for the w x output voltage 8, 9 .

4. CONCLUSION

In this article we presented a new source formulation. This new formulation allows for the FDTD simulation of highfrequency integrated circuits with and without ground planes. In most practical circuit simulations, this new source formulation is also relatively easy and convenient to use, because its relation to the actual voltage source is fairly straightforward compared to existing source formulations. In conclusion, we believe that this new source formulation adds great value to the FDTD simulation of a wide variety of high-frequency integrated circuits.