𝔖 Bobbio Scriptorium

✦ LIBER ✦

Formally Verified Argument Reduction with a Fused Multiply-Add

✍ Scribed by Boldo, S.; Daumas, M.; Ren-Cang Li

Book ID: 118698045
Publisher: IEEE
Year: 2009
Tongue: English
Weight: 866 KB
Volume: 58
Category: Article
ISSN: 0018-9340
DOI: 10.1109/tc.2008.216

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Fast pseudorandom-number generators with

Fast pseudorandom-number generators with modulus 2k or 2k-1 using fused multiply-add

✍ R. C. Agarwal; R. F. Enenkel; F. G. Gustavson; A. Kothari; M. Zubair 📂 Article 📅 2002 🏛 IBM 🌐 English ⚖ 700 KB

[IEEE 2012 IEEE International Solid- Sta

[IEEE 2012 IEEE International Solid- State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2012.02.19-2012.02.23)] 2012 IEEE International Solid-State Circuits Conference - A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS

✍ Kaul, Himanshu; Anders, Mark; Mathew, Sanu; Hsu, Steven; Agarwal, Amit; Sheikh, 📂 Article 📅 2012 🏛 IEEE ⚖ 449 KB

[IEEE 20th International Conference on V

[IEEE 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) - Bangalore, India (2007.01.6-2007.01.10)] 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) - Design of A Fully Pipelined Single-Precision Multiply-Add-Fused Unit

✍ Li, Gongqiong; Li, Zhaolin 📂 Article 📅 2007 🏛 IEEE ⚖ 467 KB