Formal Semantics and Proof Techniques for Optimizing VHDL Models

✍ Scribed by Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey (auth.)

• Publisher: Springer US
• Year: 1999
• Tongue: English
• Leaves: 168
• Edition: 1
• Category: Library

✦ Synopsis

Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions.
Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.

✦ Table of Contents

Front Matter....Pages i-xxi
Introduction....Pages 1-5
Related Work....Pages 7-15
The Static Model....Pages 17-29
A Well-Formed VHDL Model....Pages 31-42
The Reduction Algebra....Pages 43-54
Completeness of the Reduced Form....Pages 55-64
Interval Temporal Logic....Pages 65-68
The Dynamic Model....Pages 69-88
Applications of the Dynamic Model....Pages 89-98
A Framework for Proving Equivalences using PVS....Pages 99-122
Conclusions....Pages 123-125
Back Matter....Pages 127-158

✦ Subjects

Circuits and Systems; Computer Hardware; Computer-Aided Engineering (CAD, CAE) and Design; Electrical Engineering