✦ LIBER ✦

Formal hardware specification and verification using prolog

✍ Scribed by Z. Brezočnik; B. Horvat

Publisher: Elsevier Science
Year: 1989
Weight: 652 KB
Volume: 27
Category: Article
ISSN: 0165-6074
DOI: 10.1016/0165-6074(89)90040-9

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Formal specification and verification of

Formal specification and verification of microprocessor systems

✍ Jeffrey J Joyce 📂 Article 📅 1988 🏛 Elsevier Science ⚖ 926 KB

Formal Specification and Verification of

Formal Specification and Verification of Complex Systems

✍ S. Gnesi 📂 Article 📅 2003 🏛 Elsevier Science 🌐 English ⚖ 90 KB

On the formal specification and verifica

On the formal specification and verification of digital circuits

✍ Peter J. de Graaff 📂 Article 📅 1990 🏛 Elsevier Science ⚖ 546 KB

Specification and Verification using Mes

Specification and Verification using Message Sequence Charts

✍ Doron Peled 📂 Article 📅 2002 🏛 Elsevier Science 🌐 English ⚖ 125 KB

Message sequence charts is a notation used in practice by protocol designers and system engineers. In this survey, some of the recent results related to this notation, in the context of specification and automatic verification of communication protocols, are presented.

An approach to formal specification and

An approach to formal specification and verification of map-centered applications

✍ M.A.V Nelson; P.S.C Alencar; D.D Cowan 📂 Article 📅 2001 🏛 Elsevier Science 🌐 English ⚖ 150 KB

Estimating protocol performance using a

Estimating protocol performance using a formal specification model

✍ Raymond E. Miller; Zafar Ullah Chaudhry 📂 Article 📅 1999 🏛 John Wiley and Sons 🌐 English ⚖ 212 KB

This paper introduces an approach for protocol performance estimation directly from a formal model of the protocol. By using the approach presented in this paper, performance of a protocol can be quickly estimated at an early stage of protocol design. The simplicity of analysis, achieved by determin