A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage
โฆ LIBER โฆ
FinFET domino logic with independent gate keepers
โ Scribed by Sherif A. Tawfik; Volkan Kursun
- Publisher
- Elsevier Science
- Year
- 2009
- Tongue
- English
- Weight
- 626 KB
- Volume
- 40
- Category
- Article
- ISSN
- 0026-2692
No coin nor oath required. For personal study only.
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This book presents an in-depth treatment of various power reduction and speed enhancement techniques based on multiple supply and threshold voltages. A detailed discussion of the sources of power consumption in CMOS circuits will be provided whilst focusing primarily on identifying the mechanisms by