Feasibility of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

✍ Scribed by Maeda, S.; Wada, Y.; Yamamoto, K.; Komurasaki, H.; Matsumoto, T.; Hirano, Y.; Iwamatsu, T.; Yamaguchi, Y.; Ipposhi, T.; Ueda, K.; Mashiko, K.; Maegawa, S.; Inuishi, M.

• Book ID: 114538832
• Publisher: IEEE
• Year: 2001
• Tongue: English
• Weight: 200 KB
• Volume: 48
• Category: Article
• ISSN: 0018-9383
• DOI: 10.1109/16.944197