Very fast and accurate 3-D capacitance extraction is essential for interconnect optimization in VLSI ultra-deep sub-micron designs (UDSM). Parallel processing provides an approach to reducing the simulation turn-around time. This paper examines the parallelization of the well-known fast multipole-ba
β¦ LIBER β¦
FASTHENRY: a multipole-accelerated 3-D inductance extraction program
β Scribed by Kamon, M.; Ttsuk, M.J.; White, J.K.
- Book ID
- 118053871
- Publisher
- IEEE
- Year
- 1994
- Tongue
- English
- Weight
- 839 KB
- Volume
- 42
- Category
- Article
- ISSN
- 0018-9480
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